Future Coherent Interconnect Technology for Networking Applications
Simon Stanley is Founder and Principal Consultant at Earlswood Marketing Ltd., an independent market analyst and consulting company based in the U.K.
Over the last eight years, Stanley has written extensively for Heavy Reading and Light Reading. His reports and Webinars cover a variety of communications-related subjects, including LTE, IMS, ATCA, MicroTCA, 40/100-Gbit/s components, 10-Gbit/s Ethernet components, multicore processors, switch fabric chipsets, network processors, and packet optical solutions. Stanley also writes the bimonthly Heavy Reading Components Insider research newsletter, covering the latest developments in telecom silicon and subsystems.
Michael Merluzzi is a Sr. Marketing Manager in the Networking Solutions Group at LSI Corporation. He has product marketing responsibilities for integrated platform solutions and application-enabling software for LSI’s Axxia® family of multicore communications processors. Previously, he has held a variety of roles in technical marketing, applications engineering and software development.
Colin Alexander holds the position of Segment Marketing Manager within ARM. He has responsibility to promote ARM based technology for the Network Infrastructure and to work with semiconductor and eco-system partners, equipment OEM's and operators to understand their requirements and influence ARM technology accordingly. Previously Colin has held various roles in start-up to large enterprise companies working in a variety of development and marketing positions.
Coherent interconnects will be at the core of next-generation network systems and system-on-chip (SoC) devices. To meet the rapidly growing processing requirements of wireless infrastructure systems and servers, network equipment manufacturers need highly integrated SoCs with a heterogeneous mix of CPU cores. These cores need to handle a mix of general-purpose processing, packet processing, and digital signal processing (DSP) functions. The interconnect at the center of these solutions must maintain cache coherency between cores and provide a low-latency path between the cores, caches, external memory, and networking I/O.
This webinar will explore the market demands and benefits of using a low-latency, coherent interconnect at the core of a next-generation networking SoC with multiple CPU cores and hardware accelerators. It details the technical challenges and looks at a solution for a coherent interconnect with integrated cache and support for DDR3 and DDR4 memories. This webinar also describes a next-generation networking SoC architecture built around a coherent interconnect and available to OEMs as a standard product or custom solution.